1. Field of the Invention
The present invention relates to a complementary semiconductor integrated circuit device, and more particularly, to a complementary semiconductor integrated circuit device capable of decreasing a fluctuation of the potential caused by a noise included in the power supply line and/or the reference voltage line.
2. Description of the Prior Art
A conventional complementary semiconductor integrated circuit device is described by taking an inverter circuit as an example. In order to simplify the description, the construction of an inverter comprising an n-type substrate including a p-well is hereinafter described. An inverter comprising the n-type substrate including an n-well and the p-well, an inverter comprising the p-type substrate including the n-well, and an inverter comprising the p-type substrate including the n-well and the p-well may be described.
FIG. 1 is a plan view showing a conventional CMOS inverter. 2 is a sectional view taken along the line II--II. The conventional CMOS inverter is described with reference to FIGS. 1 and 2. The conventional CMOS inverter comprises a p-channel MOS transistor T.sub.P formed on an n-type semiconductor substrate 1, an n-channel MOS transistor T.sub.N formed in a p-well provided in the n-type semiconductor substrate 1, a field oxide film 3 adapted for disconnecting the p-channel MOS transistor T.sub.P from the n-channel MOS transistor T.sub.N.
The p-channel MOS transistor T.sub.P includes p-type diffusion layers 11 and 12, a gate 6 of polysilicon formed on a channel region 15 provided therebetween through an insulating film.
The n-channel MOS transistor T.sub.N includes n-type diffusion layers 13 and 14, the gate 6 of polysilicon which serves as the input of the CMOS inverter and is formed on the channel region 15 provided therebetween through the insulating film.
The P-type diffusion layer 12 which serves as the source of the p-channel MOS transistor T.sub.P is disposed adjacently to an n-type diffusion layer 4 for providing a potential to the n-type semiconductor substrate 1. An aluminum wire 7 which serves for providing supply voltage to the inverter is connected to the p-type diffusion layer 12 and the n-type diffusion layer 4 through a contact hole 10.
The n-type diffusion layer 14 which serves as the source of the n-type channel MOS transistor T.sub.N is disposed adjacently to a p-type diffusion layer 5 for providing a potential to the p-well. An aluminum wire 8 which serves for providing the reference voltage to the inverter is connected to the n-type diffusion layer 14 and the p-type diffusion layer 5.
An aluminum wire 9 which serves as the output of the CMOS inverter is connected to the p-type diffusion layer 11 which serves as the drain of the p-channel MOS transistor T.sub.P and the n-type diffusion layer 13 which serves as the drain of the n-channel MOS transistor T.sub.N
The description of the layout pattern and the equivalent circuit of an inverter circuit is omitted herein: They are described, for example, in "Principle of CMOS VLSI Design A Systems Perspective " written by Weste et al. and published by N.H.E. in 1985.
FIG. 3 shows the equivalent circuit of the inverter shown in FIGS. 1 and 2.
The inverter includes the p-channel transistor T.sub.P and the n-channel transistor T.sub.N connected in series between the power supply V.sub.DD and the reference voltage.
The operation of the inverter is described with reference to FIG. 3. The signal inputted to the inverter is applied to the gates of the p-channel MOS transistor T.sub.P and the n-channel MOS transistor T.sub.N. When a high level voltage is applied to the input terminal IN of the inverter, the n-channel MOS transistor T.sub.N is turned on and the p-channel MOS transistor T.sub.P is turned off. As a result, the inverter outputs a low level voltage. When a low level voltage is applied to the input terminal IN of the inverter, the p-channel transistor T.sub.P is turned on and the n-channel transistor T.sub.N is turned off. As a result, the inverter outputs a high level signal.
The inverter with which a conventional complementary semiconductor circuit device is equipped is constructed as above. It is to be noted that the power supply V.sub.DD ,and the reference voltage are connected directly to the sources of the p-channel transistor T.sub.P and the n-channel transistor T.sub.N, respectively.
Such a construction has a disadvantage in that a noise included in the power supply V.sub.DD or the reference voltage causes the potentials thereof to change, and the inverter functions improperly. Therefore, the development of a complementary semiconductor circuit device capable of minimizing the change of the potentials of the power supply and/or the reference voltage has been desired.